The rapid progress of quantum computing threatens many classical cryptographic schemes—including RSA and ECC—making the shift to post-quantum cryptography (PQC) urgent.
This hands-on tutorial walks you through designing and implementing a secure post-quantum RISC-V IoT platform on an FPGA.

Key features include:

• CRYSTALS-Dilithium 3 digital-signature acceleration via hardware–software co-design
• An open, extensible RISC-V architecture that easily embeds custom PQC accelerators
• Full FPGA prototyping, giving you practical experience in building and optimizing secure embedded systems for a post-quantum world

We begin with an overview of lattice-based PQC, focusing on CRYSTALS-Dilithium 3—its architecture, security properties, and the computational, memory, and power demands it places on IoT devices. You’ll see how offloading compute-intensive operations to dedicated hardware drastically improves performance while balancing flexibility, resource usage, and throughput.

Following the theory, you’ll complete a step-by-step, live FPGA build:

1. RISC-V core enhanced with a custom PQC accelerator
2. Integration with a LoRa module for low-power, long-range IoT connectivity
3. End-to-end FPGA workflow—HDL coding, block-design creation, synthesis, implementation, and bitstream generation
4. Real-time demonstration and evaluation of the finished system

To broaden your perspective, we will also briefly showcase our GPU-based lattice-PQC prototypes, outlining their design choices and performance metrics. Throughout the session, interactive discussions and live demos will give you deep insights into architectural design, hardware–software partitioning, and optimization techniques for resource-constrained, secure embedded platforms.

Why this matters: Bridging the gap between cutting-edge PQC algorithms and real-world IoT deployments equips you to build the secure systems tomorrow’s connected devices will rely on.