Mr. Xuziang WANG (Ben Wang) received his bachelor’s degree in Integrated Circuit Design and Integrated Systems from the School of Integrated Circuits, Shandong University in 2026. He joined CALAS as an FYP student in July 2026 and began research under the supervision of Prof. Ray C. C. Cheung. He has experience in FPGA development, digital logic design, Transformer operator optimization, and hardware-software co-design. His current research focuses on memory-access optimization and hardware acceleration for recurrent-state linear attention in low-latency large language model decoding.