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Hong Yan

Randomized tensor decomposition using parallel reconfigurable systems
Efficient Blind Hyperspectral Unmixing Framework Based on CUR Decomposition (CUR-HU)
RO-SVD: A Reconfigurable Hardware Copyright Protection Framework for AIGC Applications
RO-SVD: A Reconfigurable Hardware Copyright Protection Framework for AIGC Applications
A High-Performance FPGA Accelerator for CUR Decomposition
An Efficient Parallel Processor for Dense Tensor Computation
Elastic Net Constraint-Based Tensor Model for High-Order Graph Matching
A high performance hardware architecture for non-negative tensor factorization
An Efficient Application Specific Instruction Set Processor (ASIP) for Tensor Computation
Feature Selection Based on Tensor Decomposition and Object Proposal for Night-Time Multiclass Vehicle Detection
High performance hardware architecture for singular spectrum analysis of Hankel tensors
An FPGA based scalable architecture of a stochastic state point process filter (SSPPF) to track the nonlinear dynamics underlying neural spiking
Design Exploration of Geometric Biclustering for Microarray Data Analysis in Data Mining
GPU-based biclustering for microarray data analysis in neurocomputing
A Flexible and Customizable Architecture for the Relaxation Labeling Algorithm
Noise filtering and occurrence identification of mouse ultrasonic vocalization call
Hypergraph based geometric biclustering algorithm