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Manish Kumar Jaiswal

Configurable Architectures for Multi-Mode Floating Point Adders
Z-TCAM: An SRAM-based Architecture for TCAM
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division
E-TCAM: An Efficient SRAM-Based Architecture for TCAM
Series Expansion based Efficient Architectures for Double Precision Floating Point Division
Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder
Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support
Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM)
VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba Technique
Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers
Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier
FPGA Implementation of SRAM-based Ternary Content Addressable Memory
High Performance Reconfigurable Architecture for Double Precision Floating Point Division