CALAS Researchers Advance FPGA Acceleration with New Electronics Publication

Sep 29, 2025

Jeff and Alex have achieved another success with their paper on systematic HLS co-design for NTT acceleration accepted in Electronics, demonstrating continued excellence in FPGA-based cryptographic hardware research.

Congratulations are in order for Jeff and Alex, whose second paper has been accepted for publication in Electronics! Their latest work, "Systematic HLS Co-Design: Achieving Scalable and Fully-Pipelined NTT Acceleration on FPGAs," represents another significant milestone in advancing cryptographic hardware acceleration.

This achievement is particularly noteworthy as it demonstrates the team’s sustained research excellence and productivity. The paper introduces a systematic approach to high-level synthesis co-design, enabling scalable and fully-pipelined implementations of Number Theoretic Transform (NTT) operations—a critical component in post-quantum cryptographic schemes.

We extend our appreciation to Gary and Patrick for their invaluable guidance throughout this research. Their expert advice has been instrumental in shaping this innovative work that pushes the boundaries of FPGA-based acceleration techniques.

This back-to-back publication success showcases the outstanding research capabilities within our team and reinforces CALAS’s leadership in cryptographic hardware design. Well done to everyone involved!