Publications

(2024). RO-SVD: A Reconfigurable Hardware Copyright Protection Framework for AIGC Applications. 35th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2024, Hong Kong, July 24-26, 2024.

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(2024). MSCA: A Multi-Grained Sparse Convolution Accelerator for DNN Training. 35th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2024, Hong Kong, July 24-26, 2024.

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(2024). Design of Light-Weight Encryption Algorithm Based on RISC-V Platform: (PhD Forum Paper). 35th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2024, Hong Kong, July 24-26, 2024.

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(2024). Building a Learner-Centric Citywide Digital Literacy Ecosystem: Train-the-Trainer, Community-Based Learning, and Gifted Education - A Guide for Educators, Policymakers, and Stakeholders. Blended Learning. Intelligent Computing in Education - 17th International Conference on Blended Learning, ICBL 2024, Macao SAR, China, July 29 - August 1, 2024, Proceedings.

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(2024). A LoRaWAN-BLE Based AIoT Smart Farm Management and Control System. 10th IEEE World Forum on Internet of Things, WF-IoT 2024, Ottawa, ON, Canada, November 10-13, 2024.

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(2023). In-Network Aggregation with Transport Transparency for Distributed Training. Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3, ASPLOS 2023, Vancouver, BC, Canada, March 25-29, 2023.

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(2023). Image Super-Resolution and FPGA Hardware Design. IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2023, Zhengzhou, China, November 14-17, 2023.

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(2023). Homomorphic Encryption-Based System Design for Secure Data Processing. IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2023, Zhengzhou, China, November 14-17, 2023.

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(2023). CO-Detector: Towards Complex Object Detection with Cross-Part Feature Learning in Remote Sensing. IEEE International Geoscience and Remote Sensing Symposium, IGARSS 2023, Pasadena, CA, USA, July 16-21, 2023.

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(2023). Bidirectionally Deformable Motion Modulation For Video-based Human Pose Transfer. IEEE/CVF International Conference on Computer Vision, ICCV 2023, Paris, France, October 1-6, 2023.

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(2023). A Platform for Adaptive Interference Mitigation and Intent Analysis Using OpenLANE. IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2023, Zhengzhou, China, November 14-17, 2023.

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(2022). Preface. International Conference on Field-Programmable Technology, (IC)FPT 2022, Hong Kong, December 5-9, 2022.

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(2022). Message from the General Chair and Program Co-Chairs. International Conference on Field-Programmable Technology, (IC)FPT 2022, Hong Kong, December 5-9, 2022.

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(2022). Melting Glacier: A 37-Year (1984-2020) High-Resolution Glacier-Cover Record of MT. Kilimanjaro. IEEE International Geoscience and Remote Sensing Symposium, IGARSS 2022, Kuala Lumpur, Malaysia, July 17-22, 2022.

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(2022). A Versatility-Performance Balanced Hardware Architecture for Scene Text Detection. IEEE Smartworld, Ubiquitous Intelligence & Computing, Scalable Computing & Communications, Digital Twin, Privacy Computing, Metaverse, Autonomous & Trusted Vehicles, SmartWorld/UIC/ScalCom/DigitalTwin/PriComp/Meta 2022, Haikou, China, December 15-18, 2022.

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(2022). A High-Performance FPGA Accelerator for CUR Decomposition. 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022, Belfast, United Kingdom, August 29 - Sept. 2, 2022.

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(2021). On the Suitability of Read only Memory for FPGA-Based CAM Emulation Using Partial Reconfiguration. Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Virtual Event, June 29-30, 2021, Proceedings.

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(2021). LoRaWAN-based Camera with (CIRA) Compression and Image Recovery Algorithm. 7th IEEE World Forum on Internet of Things, WF-IoT 2021, New Orleans, LA, USA, June 14 - July 31, 2021.

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(2021). Design of a Battery Carrying Barge for Enhancing Autonomous Sailboat's Endurance Capacity. IEEE International Conference on Real-time Computing and Robotics, RCAR 2021, Xining, China, July 15-19, 2021.

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(2021). An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics. 31st International Conference on Field-Programmable Logic and Applications, FPL 2021, Dresden, Germany, August 30 - Sept. 3, 2021.

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(2021). Aero-Hydroponic Agriculture IoT System. 7th IEEE World Forum on Internet of Things, WF-IoT 2021, New Orleans, LA, USA, June 14 - July 31, 2021.

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(2020). Dynamic Sparse Training: Find Efficient Sparse Network From Scratch With Trainable Masked Layers. 8th International Conference on Learning Representations, ICLR 2020, Addis Ababa, Ethiopia, April 26-30, 2020.

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(2020). A Highly Parallel Constant-Time Almost-Inverse Algorithm. IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2020, Macau, SAR, China, August 21-24, 2020.

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(2019). Reconfigurable RISC-V Secure Processor And SoC Integration. IEEE International Conference on Industrial Technology, ICIT 2019, Melbourne, Australia, February 13-15, 2019.

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(2019). Optimized Polynomial Multiplier Over Commutative Rings on FPGAs: A Case Study on BIKE. International Conference on Field-Programmable Technology, FPT 2019, Tianjin, China, December 9-13, 2019.

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(2019). High Performance Power-Efficient Gate-Based CAM for Reconfigurable Computing. 15th International Conference on Mobile Ad-Hoc and Sensor Networks, MSN 2019, Shenzhen, China, December 11-13, 2019.

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(2019). Bank-selective Strategy for Gate-based Ternary Content-addressable Memory on FPGAs. 30th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2019, New York, NY, USA, July 15-17, 2019.

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(2019). An Efficient Application Specific Instruction Set Processor (ASIP) for Tensor Computation. 30th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2019, New York, NY, USA, July 15-17, 2019.

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(2019). Accurate and Compact Convolutional Neural Networks with Trained Binarization. 30th British Machine Vision Conference 2019, BMVC 2019, Cardiff, UK, September 9-12, 2019.

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(2018). Lightweight Secure Processor Prototype on FPGA. 28th International Conference on Field Programmable Logic and Applications, FPL 2018, Dublin, Ireland, August 27-31, 2018.

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(2017). High DC gain and wide output swing class-C inverter. International SoC Design Conference, ISOCC 2017, Seoul, South Korea, November 5-8, 2017.

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(2017). Fast HEVC intra coding decision based on statistical cost and corner detection. International Conference on Systems, Signals and Image Processing, IWSSIP 2017, Poznań, Poland, May 22-24, 2017.

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(2014). Zero collision attack and its countermeasures on Residue Number System multipliers. 2014 International Symposium on Integrated Circuits (ISIC), Singapore, December 10-12, 2014.

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(2014). Trade-offs between the sensitivity and the speed of the FPGA-based sequence aligner. 2014 International Symposium on Integrated Circuits (ISIC), Singapore, December 10-12, 2014.

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(2014). Time-efficient computation of digit serial Montgomery multiplication. 2014 International Symposium on Integrated Circuits (ISIC), Singapore, December 10-12, 2014.

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(2014). Laguerre-volterra model and architecture for MIMO system identification and output prediction. 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2014, Chicago, IL, USA, August 26-30, 2014.

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(2014). Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division. IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, July 9-11, 2014.

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(2014). Big data genome sequencing on Zynq based clusters (abstract only). The 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA ‘14, Monterey, CA, USA - February 26 - 28, 2014.

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(2014). A complementary architecture for high-speed true random number generator. 2014 International Conference on Field-Programmable Technology, FPT 2014, Shanghai, China, December 10-12, 2014.

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(2013). Noise filtering and occurrence identification of mouse ultrasonic vocalization call. International Conference on Machine Learning and Cybernetics, ICMLC 2013, Tianjin, China, July 14-17, 2013.

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(2013). Genome sequencing using mapreduce on FPGA with multiple hardware accelerators (abstract only). The 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA ‘13, Monterey, CA, USA, February 11-13, 2013.

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(2013). FPGA IP protection by binding Finite State Machine to Physical Unclonable Function. 23rd International Conference on Field programmable Logic and Applications, FPL 2013, Porto, Portugal, September 2-4, 2013.

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(2013). Fast simulation of Digital Spiking Silicon Neuron model employing reconfigurable dataflow computing. 2013 International Conference on Field-Programmable Technology, FPT 2013, Kyoto, Japan, December 9-11, 2013.

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(2013). Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM). 23rd International Conference on Field programmable Logic and Applications, FPL 2013, Porto, Portugal, September 2-4, 2013.

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(2013). Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits. 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2013, Seattle, WA, USA, April 28-30, 2013.

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(2013). A reconfigurable architecture for real-time prediction of neural activity. 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013.

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(2013). A customizable Stochastic State Point Process Filter (SSPPF) for neural spiking activity. 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2013, Osaka, Japan, July 3-7, 2013.

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(2012). Low complexity and hardware-friendly spectral modular multiplication. 2012 International Conference on Field-Programmable Technology, FPT 2012, Seoul, Korea (South), December 10-12, 2012.

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(2012). High Performance Reconfigurable Architecture for Double Precision Floating Point Division. Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Hong Kong, China, March 19-23, 2012. Proceedings.

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(2012). GPU-Based Biclustering for Neural Information Processing. Neural Information Processing - 19th International Conference, ICONIP 2012, Doha, Qatar, November 12-15, 2012, Proceedings, Part V.

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(2012). FPGA Implementation of SRAM-based Ternary Content Addressable Memory. 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, IPDPS 2012, Shanghai, China, May 21-25, 2012.

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(2012). Faster Pairing Coprocessor Architecture. Pairing-Based Cryptography - Pairing 2012 - 5th International Conference, Cologne, Germany, May 16-18, 2012, Revised Selected Papers.

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(2012). Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier. 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, IPDPS 2012, Shanghai, China, May 21-25, 2012.

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(2012). Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers. 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2012, 29 April - 1 May 2012, Toronto, Ontario, Canada.

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(2012). An FPGA-based acceleration platform for auction algorithm. 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012.

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(2012). A dual mode FPGA design for the hippocampal prosthesis. Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2012, San Diego, CA, USA, August 28 - September 1, 2012.

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(2011). Rapid single-chip secure processor prototyping on the OpenSPARC FPGA platform. Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, RSP 2011, Karlsruhe, Germany, 24-27 May, 2011.

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(2011). Hydrate: Hybrid Reconfigurable Architecture Expressions. 2011 International Conference on Field-Programmable Technology, FPT 2011, New Delhi, India, December 12-14, 2011.

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(2011). FPGA Implementation of Pairings Using Residue Number System and Lazy Reduction. Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28 - October 1, 2011. Proceedings.

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(2011). FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Spiking Activities. IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011, Salt Lake City, Utah, USA, 1-3 May 2011.

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(2011). FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Activities. International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece.

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(2011). A hardware-based computational platform for Generalized Laguerre-Volterra MIMO model for neural activities. 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2011, Boston, MA, USA, August 30 - Sept. 3, 2011.

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(2010). Reconfigurable Number Theoretic Transform architectures for cryptographic applications. Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China.

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(2010). Design Automation for Reconfigurable Interconnection Networks. Reconfigurable Computing: Architectures, Tools and Applications, 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010. Proceedings.

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(2010). Counter Embedded Memory architecture for trusted computing platform. Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, RSP 2010, Fairfax, VA, USA, 8-11 June, 2010.

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(2009). A High-Performance Hardware Architecture for Spectral Hash Algorithm. 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA.

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(2007). Instrumented Multi-Stage Word-Length Optimization. 2007 International Conference on Field-Programmable Technology, ICFPT 2007, Kitakyushu, Japan, December 12-14, 2007.

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(2007). Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems. FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007.

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(2006). Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation. 2006 IEEE International Conference on Field Programmable Technology, FPT 2006, Bangkok, Thailand, December 13-15, 2006.

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(2005). Ziggurat-based Hardware Gaussian Random Number Generator. Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005.

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(2005). Reconfigurable Elliptic Curve Cryptosystems on a Chip. 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany.

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(2005). Reconfigurable Acceleration for Monte Carlo Based Financial Simulation. Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, FPT 2005, 11-14 December 2005, Singapore.

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(2005). Automating custom-precision function evaluation for embedded processors. Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005.

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(2004). On Optimal Irregular Switch Box Designs. Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings.

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(2004). Customising Hardware Designs for Elliptic Curve Cryptography. Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings.

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(2004). A System on Chip Design Framework for Prime Number Validation Using Reconfigurable Hardware. Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings.

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(2004). A scalable hardware architecture for prime number validation. Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, Brisbane, Australia, December 6-8, 2004.

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(2003). An FPGA-based re-configurable 24-bit 96kHz sigma-delta audio DAC. Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, Tokyo, Japan, FPT 2003, December 15-17, 2003.

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(2002). On Optimum Designs of Universal Switch Blocks. Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings.

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(2001). On Optimum Switch Box Designs for 2-D FPGAs. Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001.

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(2001). Further improve circuit partitioning using GBAW logic perturbation techniques. Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001.

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(2000). On improved graph-based alternative wiring scheme for multi-level logic optimization. Proceedings of the 2000 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000, Jounieh, Lebanon, December 17-20, 2000.

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