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Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support

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Design Automation Framework for Reconfigurable Interconnection Networks

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HEALPIX DCT technique for compressing PCA-based illumination adjustable images

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Parallel architecture for DNA sequence inexact matching with Burrows-Wheeler Transform

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Real-Time Prediction of Neuronal Population Spiking Activity Using FPGA

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VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba Technique

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Hypergraph based geometric biclustering algorithm

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Subthreshold CMOS voltage reference circuit with body bias compensation for process variation

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A High Speed Pairing Coprocessor Using RNS and Lazy Reduction

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High-Performance and Scalable System Architecture for the Real-Time Estimation of Generalized Laguerre-Volterra MIMO Model From Neural Population Spiking Activity

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