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Series Expansion based Efficient Architectures for Double Precision Floating Point Division

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Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder

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A (σ)(δ) modulator using gain-Boost Class-C Inverter for Audio Applications

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A 0.8-V 230-(µ)W 98-dB DR Inverter-Based (Σ)(Δ) Modulator for Audio Applications

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A Flexible and Customizable Architecture for the Relaxation Labeling Algorithm

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A memory-based NFA regular expression match engine for signature-based intrusion detection

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A scalable RNS Montgomery multiplier over F(_mbox2(^mboxm))

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Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support

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Design Automation Framework for Reconfigurable Interconnection Networks

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HEALPIX DCT technique for compressing PCA-based illumination adjustable images

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