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A Flexible and Customizable Architecture for the Relaxation Labeling Algorithm

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A memory-based NFA regular expression match engine for signature-based intrusion detection

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A scalable RNS Montgomery multiplier over F(_mbox2(^mboxm))

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Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support

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Design Automation Framework for Reconfigurable Interconnection Networks

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HEALPIX DCT technique for compressing PCA-based illumination adjustable images

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Parallel architecture for DNA sequence inexact matching with Burrows-Wheeler Transform

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Real-Time Prediction of Neuronal Population Spiking Activity Using FPGA

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VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba Technique

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Hypergraph based geometric biclustering algorithm

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