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Subthreshold CMOS voltage reference circuit with body bias compensation for process variation

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A High Speed Pairing Coprocessor Using RNS and Lazy Reduction

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High-Performance and Scalable System Architecture for the Real-Time Estimation of Generalized Laguerre-Volterra MIMO Model From Neural Population Spiking Activity

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Hierarchical Segmentation for Hardware Function Evaluation

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Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations

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A Flexible Architecture for Precise Gamma Correction

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Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method

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The exact channel density and compound design for generic universal switch blocks

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Accuracy-Guaranteed Bit-Width Optimization

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Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes

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