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Toward Practical Code-Based Signature: Implementing Fast and Compact QC-LDGM Signature Scheme on Embedded Hardware

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An FPGA-Based High-Performance Neural Ensemble Spiking Activity Simulator Utilizing Generalized Volterra Kernel and Complexity Analysis

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FPGA-Based High-Performance Collision Detection: An Enabling Technique for Image-Guided Robotic Surgery

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Parameter Space for the Architecture of FFT-Based Montgomery Modular Multiplication

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A Fast CU Size Decision Algorithm for the HEVC Intra Encoder

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An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics

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Architecture Support for Task Out-of-Order Execution in MPSoCs

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Configurable Architectures for Multi-Mode Floating Point Adders

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Efficient Pairing Computation on Huff Curves

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Fast and Generic Inversion Architectures Over GF(2(^mboxm)) Using Modified Itoh-Tsujii Algorithms

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