Article-Journal

A Bias-Bounded Digital True Random Number Generator Architecture

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
A Fully Pipelined Hardware Architecture for Intra Prediction of HEVC

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
A low power V-band LC VCO with high Q varactor technique in 40 nm CMOS process

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
Area-Time Efficient Architecture of FFT-Based Montgomery Multiplication

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
Area-Time Efficient Computation of Niederreiter Encryption on QC-MDPC Codes for Embedded Hardware

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
Compact Constant Weight Coding Engines for the Code-Based Cryptography

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
Toward Practical Code-Based Signature: Implementing Fast and Compact QC-LDGM Signature Scheme on Embedded Hardware

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
An FPGA-Based High-Performance Neural Ensemble Spiking Activity Simulator Utilizing Generalized Volterra Kernel and Complexity Analysis

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
FPGA-Based High-Performance Collision Detection: An Enabling Technique for Image-Guided Robotic Surgery

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
Parameter Space for the Architecture of FFT-Based Montgomery Modular Multiplication

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL