Paper-Conference

Reconfigurable RISC-V Secure Processor And SoC Integration

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Zhenya Zang, Yao Liu, Ray C. C. Cheung

Lightweight Secure Processor Prototype on FPGA

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Yao Liu, Ray C. C. Cheung, Hei Wong

Fast HEVC intra coding decision based on statistical cost and corner detection

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Biao Min, Zhe Xu, Ray C. C. Cheung

High DC gain and wide output swing class-C inverter

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Yaya Chen, Yan Han, Shifeng Zhang, Tianlin Cao, Xiaoxia Han, Ray C. C. Cheung

A complementary architecture for high-speed true random number generator

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Xian Yang, Ray C. C. Cheung

Big data genome sequencing on Zynq based clusters (abstract only)

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Chao Wang, Xi Li, Xuehai Zhou, Yunji Chen, Ray C. C. Cheung

Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division

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Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul

Laguerre-volterra model and architecture for MIMO system identification and output prediction

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Will X. Y. Li, Yao Xin, Rosa H. M. Chan, Dong Song, Theodore W. Berger, Ray C. C. Cheung

Time-efficient computation of digit serial Montgomery multiplication

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Wangchen Dai, Huapeng Wu, Ray C. C. Cheung

Trade-offs between the sensitivity and the speed of the FPGA-based sequence aligner

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Peng Chen, Chao Wang, Xi Li, Xuehai Zhou, Aili Wang, Ray C. C. Cheung