Paper-Conference

An Efficient Application Specific Instruction Set Processor (ASIP) for Tensor Computation

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Bank-selective Strategy for Gate-based Ternary Content-addressable Memory on FPGAs

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High Performance Power-Efficient Gate-Based CAM for Reconfigurable Computing

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Optimized Polynomial Multiplier Over Commutative Rings on FPGAs: A Case Study on BIKE

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Reconfigurable RISC-V Secure Processor And SoC Integration

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Lightweight Secure Processor Prototype on FPGA

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Fast HEVC intra coding decision based on statistical cost and corner detection

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High DC gain and wide output swing class-C inverter

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A complementary architecture for high-speed true random number generator

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Big data genome sequencing on Zynq based clusters (abstract only)

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