Paper-Conference

High DC gain and wide output swing class-C inverter

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
A complementary architecture for high-speed true random number generator

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
Big data genome sequencing on Zynq based clusters (abstract only)

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
Laguerre-volterra model and architecture for MIMO system identification and output prediction

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
Time-efficient computation of digit serial Montgomery multiplication

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
Trade-offs between the sensitivity and the speed of the FPGA-based sequence aligner

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
VLSI architecture of a high-performance neural spiking activity simulator based on generalized Volterra kernel

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
Zero collision attack and its countermeasures on Residue Number System multipliers

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL
A customizable Stochastic State Point Process Filter (SSPPF) for neural spiking activity

Add the full text or supplementary notes for the publication here using Markdown formatting.

Cite DOI URL