Paper-Conference

Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division

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Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul

Laguerre-volterra model and architecture for MIMO system identification and output prediction

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Will X. Y. Li, Prof. Yao XIN, Rosa H. M. Chan, Dong Song, Theodore W. Berger, Ray C. C. Cheung

Time-efficient computation of digit serial Montgomery multiplication

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Wangchen Dai, Huapeng Wu, Ray C. C. Cheung

Trade-offs between the sensitivity and the speed of the FPGA-based sequence aligner

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Peng Chen, Chao Wang, Xi Li, Xuehai Zhou, Aili Wang, Ray C. C. Cheung

VLSI architecture of a high-performance neural spiking activity simulator based on generalized Volterra kernel

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Will X. Y. Li, Prof. Yao XIN, Dong Song, Theodore W. Berger, Ray C. C. Cheung

Zero collision attack and its countermeasures on Residue Number System multipliers

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Marc Stöttinger, Gavin Xiaoxu Yao, Ray C. C. Cheung

A customizable Stochastic State Point Process Filter (SSPPF) for neural spiking activity

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Prof. Yao XIN, Will X. Y. Li, Biao Min, Yan Han, Ray C. C. Cheung

A reconfigurable architecture for real-time prediction of neural activity

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Will X. Y. Li, Ray C. C. Cheung, Rosa H. M. Chan, Dong Song, Theodore W. Berger

Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits

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Jiliang Zhang, Yaping Lin, Yongqiang Lu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian

Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM)

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Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung