Paper-Conference

A reconfigurable architecture for real-time prediction of neural activity

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Will X. Y. Li, Ray C. C. Cheung, Rosa H. M. Chan, Dong Song, Theodore W. Berger

Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits

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Jiliang Zhang, Yaping Lin, Yongqiang Lu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian

Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM)

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Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung

Fast simulation of Digital Spiking Silicon Neuron model employing reconfigurable dataflow computing

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Will X. Y. Li, Shridhar Chaudhary, Ray C. C. Cheung, Takeshi Matsumoto, Masahiro Fujita

FPGA IP protection by binding Finite State Machine to Physical Unclonable Function

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Jiliang Zhang, Yaping Lin, Yongqiang Lyu, Gang Qu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian

Genome sequencing using mapreduce on FPGA with multiple hardware accelerators (abstract only)

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Chao Wang, Xi Li, Xuehai Zhou, Jim Martin, Ray C. C. Cheung

Noise filtering and occurrence identification of mouse ultrasonic vocalization call

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Nancy Yu Song, Jerome Nicon, Biao Min, Ray C. C. Cheung, M. Ashraful Amin, Hong Yan

A dual mode FPGA design for the hippocampal prosthesis

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Will X. Y. Li, Rosa H. M. Chan, Dong Song, Theodore W. Berger, Ray C. C. Cheung

An FPGA-based acceleration platform for auction algorithm

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Pengfei Zhu, Chun Zhang, Hua Li, Ray C. C. Cheung, Bryan Hu

Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers

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Manish Kumar Jaiswal, Ray C. C. Cheung