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A scalable hardware architecture for prime number validation

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A System on Chip Design Framework for Prime Number Validation Using Reconfigurable Hardware

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Customising Hardware Designs for Elliptic Curve Cryptography

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On Optimal Irregular Switch Box Designs

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An FPGA-based re-configurable 24-bit 96kHz sigma-delta audio DAC

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On Optimum Designs of Universal Switch Blocks

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Further improve circuit partitioning using GBAW logic perturbation techniques

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On Optimum Switch Box Designs for 2-D FPGAs

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On improved graph-based alternative wiring scheme for multi-level logic optimization

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