Application-Specific Architectures on FPGAs: From Low-Latency Computing to Unconventional Computing

Field-programmable gate arrays (FPGAs) are often viewed primarily as hardware accelerators. However, one of their most distinctive capabilities is the possibility of tailoring the computing architecture itself to the structure, dataflow, and timing requirements of a problem. This presentation explores this perspective through several research directions developed at Polytechnique Montreal. The first part focuses on FPGA-based real-time simulation of power electronics, where deterministic low-latency execution, rather than throughput alone, is a fundamental requirement. Recent developments in specialized solver architectures and accurate simulation of high-switching-frequency converters will be presented. The second part examines programmable packet processing, where domain-specific P4 descriptions can be mapped onto deeply pipelined FPGA architectures optimized for streaming computation and data locality. Finally, the presentation moves beyond conventional computational models and introduces FPGA-based stochastic Ising machines for combinatorial optimization. Recent work on a scalable, data-driven architecture and on metaheuristic extensions improving solution quality and time-to-solution will be discussed. Across these applications, the presentation highlights common architectural principles including spatial parallelism, pipelining, customized numerical representations, data locality, deterministic timing, and hardware-algorithm co-design, illustrating how FPGAs can enable forms of specialized computing that go beyond conventional acceleration.

Tarek Ould-Bachir received the B.Eng., M.Sc.A., and Ph.D. degrees in Electrical Engineering from Polytechnique Montreal, Canada, in 2005, 2008, and 2013, respectively. He is an Associate Professor in the Department of Computer and Software Engineering at Polytechnique Montreal, where his research focuses on application-specific computing architectures, FPGA and heterogeneous computing, real-time simulation, programmable networking, and unconventional computing. Prior to joining academia, he spent more than a decade at OPAL-RT Technologies, where he contributed to the development of high-performance FPGA-based real-time simulation technologies. His current research explores the use of specialized hardware architectures for low-latency numerical computation, programmable data-plane processing, and combinatorial optimization. He currently serves as Chair of the IEEE Industrial Electronics Society Technical Committee on Electronic Systems-on-Chip (ESOC) and is co-founder and President of Solutions Rexys Inc.