A Programming Model for Composable Accelerator Design

Designing high-performance hardware accelerators requires navigating a complex trade-off between programming productivity and hardware efficiency. Traditional high-level synthesis (HLS) tools often couple algorithm specifications with hardware implementation details, making it difficult to explore architectural optimizations while maintaining modularity and reuse. In this talk, I will present Allo, a programming model for composable accelerator design that separates algorithmic descriptions from hardware customization. Allo introduces a structured, modular approach to hardware generation, enabling developers to independently optimize different components of a design and compose them into complete accelerators. I will discuss the key abstractions and compiler techniques behind Allo, how they facilitate hardware specialization and design-space exploration, and how the framework enables efficient accelerator implementations across diverse workloads.

Niansong Zhang is a PhD student at Cornell University advised by Prof. Zhiru Zhang. His research spans accelerator design and programming models, dataflow and compute-in-memory architectures, and agentic electronic design automation. His work has been recognized with four best paper awards at TRETS 2023 and 2026, FPGA 2024, and ISPD 2025, along with best paper nominations at FPGA 2025 and FPL 2020.